The Custom Silicon Race: Everyone Wants Their Own AI Chip

At the Hot Chips 2026 conference, a clear theme emerged: the era of relying on a handful of standard GPU designs for all AI workloads is ending. From OpenAI's in-house inference ASIC to AMD's acquisition of etched-silicon technology, to Cerebras's wafer-scale systems, companies are building custom silicon tailored to their specific AI needs.

This is not a marginal trend. It reflects a structural shift in how AI infrastructure is designed and deployed. As AI workloads diverge — training vs. inference vs. agentic interaction vs. bulk throughput — a single chip architecture increasingly leaves performance and efficiency on the table. Custom silicon lets companies optimize for exactly what their workloads need.

OpenAI's Jalapeño: inference, purpose-built

OpenAI used Hot Chips 2026 to fully detail Jalapeño, its first custom inference AI accelerator co-developed with Broadcom. The ASIC is designed around a specific premise: the best AI accelerator is not necessarily the one with the highest peak arithmetic rate, but the one that completes real requests with the lowest latency and energy.

OpenAI positions Jalapeño as an inference platform rather than a raw accelerator. The chip reportedly outperforms NVIDIA's GB300 in OpenAI's first published benchmarks, delivering more performance at half the power (700W vs. 1400W). It is part of OpenAI's plan to build 10 GW of AI infrastructure by 2029. First chips are planned for end of 2026, with a multi-year ramp — and it is vertically integrated, meaning no one outside OpenAI can rent or access it directly.

AMD's etched-silicon bet

AMD's acquisition of Taalas represents the opposite architectural bet. Rather than building bigger wafer-scale systems, Taalas etches model weights directly into silicon — a technique their HC1 test chip claimed beat Cerebras's prior-generation CS-3 by 8.5× on raw tokens per second. The tradeoff: you cannot update the model without fabricating new silicon. But for workloads where the model is stable and inference speed is paramount, etched silicon offers performance that reconfigurable architectures cannot match.

Cerebras: wafer-scale at full production

Cerebras's CS-4 (covered in detail elsewhere on this site) extends the wafer-scale approach to three WSE-3 Turbo processors per rack, with the Nexus platform architecture and sub-2-microsecond wafer-to-wafer latency. The company frames this as the inference era's infrastructure — not training, but the fast, interactive decode that agentic systems need.

Why the race is on

Three factors are driving the custom silicon trend. First, GPU economics: NVIDIA's dominant position means companies are paying premium prices and facing supply constraints for hardware that was designed for a broad range of workloads, not their specific one. Second, workload specialization: as AI applications diverge into training, inference, agentic interaction, and edge deployment, one-size-fits-all hardware leaves performance on the table. Third, sovereignty and control: companies and nations want hardware supply chains they control, not dependent on a single vendor's roadmap and export-controlled supply.

The result is a Cambrian explosion of AI chip architectures — wafer-scale, etched silicon, HBM4-based ASICs, LPU (language processing unit) designs, neuromorphic processors, and RISC-V chips with integrated AI acceleration. None of these has definitively won, and the field is still early. But the direction is clear: the AI hardware landscape of 2026 is no longer a GPU market. It is a custom silicon market, and every major player is building their own.