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Arm Enters the Data Center with Its First Server CPU

At Hot Chips 2026, Arm revealed detailed specifications for its AGI data center CPU — the company's first complete commercial CPU design, built for AI servers and agentic AI systems. The processor marks a significant shift for Arm: rather than licensing its instruction set architecture to other companies, Arm is now designing and shipping its own server silicon.

The AGI is a dual-chiplet processor built on TSMC's N3P process, packing up to 136 Neoverse V3 cores running at 2.80–3.70 GHz, with 2 MB of L2 cache per core, 128-bit SVE2 vector engines, and up to 272 MB of system-level cache. Each chiplet contains 50 billion transistors and 70 V3 cores, with four redundant cores added for yield — meaning the physical die has 144 cores but the product exposes up to 136.

An unconventional design

The AGI's design choices buck several industry trends. Rather than the heterogeneous multi-chiplet approach used by AMD, Intel, and NVIDIA — where compute and I/O are separated onto different dies — Arm chose two largely self-contained SoC chiplets that place both compute and I/O on the same die.

This decision is fundamental to the processor's memory performance. With compute and memory controllers on the same die, memory traffic does not need to travel to another chiplet to reach a memory controller. The result: enormous memory bandwidth (844.8 GB/s with DDR5-8800, though that memory speed has yet to reach the market) combined with latency under 100 nanoseconds. Arm's goal is to optimize for memory locality, bandwidth, and latency — not exactly for compute performance density or manufacturing modularity the way AMD's EPYC architecture does.

Each chiplet uses an 8×9 CMN-S3 mesh interconnect to connect CPU cores, memory, I/O, and accelerators, incorporating a 128 MB distributed system-level cache with snoop filtering and hierarchical caching through a Super Home Node (HN-S) — logic that acts as a distribution center for handling traffic across the chip. Critically, Arm designed the coherent system to extend outside the die, extending coherency beyond the socket in a concept closer to Intel's distributed Xeon 2D mesh than AMD's Infinity Fabric approach.

Built for agentic AI and latency-sensitive workloads

Arm positions the AGI primarily for AI servers and agentic AI systems. Memory performance is particularly important for agentic AI workloads, where many small requests with low latency requirements characterize the workload. The AGI's capable coherent NUMA memory subsystem features two six-channel DDR5 subsystems per chiplet, with support for fully out-of-order command scheduling, bank-parallelism-optimized address mapping, and programmable page policies to improve DRAM utilization.

Anti-starvation mechanisms help maintain predictable service under heavy load, and extensive RAS (reliability, availability, serviceability) capabilities include single-DRAM-device failure correction with Chipkill-class protection, memory scrubbing, row-hammer mitigation, and error logging. Arm also implements memory-bandwidth limiting and monitoring through Memory Partitioning and Monitoring (MPAM) with QoS-based traffic prioritization.

The memory bandwidth story

Arm's emphasis on memory bandwidth per core is notable: the AGI supports DDR5-8800, providing roughly 6 GB/s of bandwidth per core. That is a significant figure, and it reflects the reality that for many AI workloads — particularly agentic inference — memory bandwidth, not raw compute, is the determining factor in performance.

The DDR5 controllers within the AGI are sophisticated: fully out-of-order command scheduling, bank-parallelism-optimized address mapping, programmable page policies, and anti-starvation mechanisms. The NUMA subsystem allows memory attached to the other chiplet to be reached across the coherent die-to-die connection, though at a latency cost — Arm's design goal is to keep as much traffic local as possible.

The performance question

Arm has not published conventional benchmark results — no SPEC CPU2017, SPECrate, or direct socket-to-socket comparisons against AMD EPYC or Intel Xeon processors. The main performance claim is "2× performance per rack versus the latest x86 platforms," based on Arm's estimates — an unconventional metric that follows NVIDIA's approach of comparing per-rack rather than per-socket performance.

The AGI is on track for commercial shipments starting in late 2026. The processor represents the first step in what Arm describes as a long-term hardware commitment, with an extensive SoC roadmap for future generations of data center processors.

What this means for the industry

Arm entering the server CPU market directly — rather than only licensing IP — changes the competitive dynamics of the data center. For years, the server CPU market has been a duopoly between Intel Xeon and AMD EPYC. Arm's AGI, alongside the growing ecosystem of Arm-based server chips from Ampere, AWS Graviton, and others, adds a third force that is architecturally distinct — optimized for memory bandwidth and latency rather than raw compute density, and built for the agentic AI workloads that are increasingly defining the data center's future.